1. Field of the Invention
The present invention relates to a solid-state imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2013-001142, filed Jan. 8, 2013, the content of which is incorporated herein by reference.
2. Description of Related Art
Recently, complementary metal oxide semiconductor (CMOS) image sensors have received attention and been practically used as solid-state imaging apparatuses. While a charge coupled device (CCD) image sensor is manufactured through a dedicated manufacturing process, the CMOS image sensor can be manufactured using a general semiconductor manufacturing process. Because of this, the CMOS image sensor, for example, can implement multiple functions by embedding various functional circuits in a sensor as in a system on chip (SOC).
Recently, as a solid-state imaging apparatus mounted on a digital camera, a digital video camera, or an endoscope, the number of examples in which a solid-state imaging apparatus with a built-in analog-to-digital converter (hereinafter referred to as an “A/D conversion circuit”) is used, for example, as in Japanese Unexamined Patent Application, First Publication No. 2011-166235 and Japanese Unexamined Patent Application, First Publication No. 2011-166197, has increased. In the A/D conversion circuit embedded in such a solid-state imaging apparatus, a ramp type A/D conversion circuit may be used. In the following description, the A/D conversion circuit is assumed to be the ramp type A/D conversion circuit.
FIG. 7 is a block diagram illustrating a schematic configuration of a solid-state imaging apparatus of the related art. The solid-state imaging apparatus 800 of the related art illustrated in FIG. 7 includes a vertical scanning circuit 801, a pixel array unit 802, an analog signal processing circuit 803, a reference signal generation circuit (hereinafter referred to as a “digital-to-analog converter (DAC)”) 804, a clock generation circuit 805, a column A/D conversion circuit 806, a horizontal scanning circuit 807, and a control circuit 808.
In the solid-state imaging apparatus 800, the analog signal processing circuit 803 generates an analog signal Vin by canceling noise from a pixel signal Vp output from each pixel 81 within the pixel array unit 802. Then, respective A/D conversion circuits 809 provided in the column A/D conversion circuit 806 perform A/D conversion on respective analog signals Vin generated by the analog signal processing circuit 803 and sequentially output A/D conversion results as digital signals DOUT.
According to a control signal input from the control circuit 808, the vertical scanning circuit 801 selects each pixel 81 within the pixel array unit 802 in units of rows of the pixel array unit 802, and causes a pixel signal Vp generated by each pixel 81 of the selected row to be output to the analog signal processing circuit 803. In the following description, a period until the next row is selected after a certain row of the pixel array unit 802 is selected is referred to as a “horizontal period.”
The pixel array unit 802 is a pixel array two-dimensionally disposed in a horizontal direction (a transverse direction in FIG. 7) and a vertical direction (a longitudinal direction in FIG. 7) of the solid-state imaging apparatus 800. Each of pixels 81 includes a photodiode, and generates a photoelectrical conversion signal (pixel signal) Vp corresponding to an amount of incident light within a fixed accumulation time. Then, the pixel array unit 802 outputs the pixel signal Vp generated by the selected pixel 81 to the analog signal processing circuit 803 according to selection from the vertical scanning circuit 801.
The analog signal processing circuit 803 amplifies the noise-canceled pixel signal Vp after canceling noise such as reset noise or 1/f noise from the pixel signal Vp input from the pixel array unit 802 according to a control signal input from the control circuit 808. Then, the analog signal processing circuit 803 outputs the amplified noise-canceled pixel signal Vp as the analog signal Vin to the column A/D conversion circuit 806.
According to the control signal input from the control circuit 808, the DAC 804 generates a ramp wave Vramp whose voltage value varies at a fixed ratio according to time in each horizontal period, and outputs the generated ramp wave Vramp to the column A/D conversion circuit 806.
The clock generation circuit 805 generates a plurality of clocks (hereinafter referred to as “multi-phase clocks”) DU having different phases from each other at fixed intervals to be used when the column A/D conversion circuit 806 performs A/D conversion. Then, the clock generation circuit 805 outputs each of the generated multi-phase clocks DU to the column A/D conversion circuit 806.
The column A/D conversion circuit 806 includes a plurality of A/D conversion circuits 809 equal in number to columns of the pixel array unit 802, wherein the plurality of A/D conversion circuits 809 have the same configuration including a comparator 82 and a data processing circuit 900. Each of the A/D conversion circuits 809 provided in the columns of the pixel array unit 802 performs a process in which the comparator 82 compares a voltage value of the input analog signal Vin to a voltage value of the ramp wave Vramp (hereinafter simply referred to as a “comparison process”) in a horizontal period. Then, the data processing circuit 900 digitizes (binarizes) a time from a timing of an initial value of the ramp wave Vramp to a timing at which the comparison process of the comparator 82 has been completed based on the multi-phase clock DU. Thereby, a digital signal DOUT corresponding to a magnitude of the analog signal Vin input to each A/D conversion circuit 809 is generated.
The horizontal scanning circuit 807 selects digital signals DOUT obtained after the respective A/D conversion circuit 809 provided inside the column A/D conversion circuit 806 has performed A/D conversion in units of columns of the pixel array unit 802, and sequentially outputs the digital signals DOUT of selected columns as outputs of the solid-state imaging apparatus 800.
Here, the data processing circuit 900 provided in the A/D conversion circuit 809 in the solid-state imaging apparatus 800 of the related art will be described. FIG. 8 is a block diagram illustrating a schematic configuration of the data processing circuit 900 within the A/D conversion circuit 809 provided in the solid-state imaging apparatus 800 of the related art. The data processing circuit 900 of the related art illustrated in FIG. 8 includes a latch unit 901 and a digital generation unit 902 (see Japanese Unexamined Patent Application, First Publication No. 2011-166235).
The data processing circuit 900 holds a phase state of a multi-phase clock in the latch unit 901 at a timing at which the comparator 82 has completed the comparison process, and the held phase state of the held multi-phase clock is digitized by the digital generation unit 902. Thereby, a binarized digital signal is generated and output. In the following description, a number shown in “[ ]: brackets” following a reference sign represents a bit of each signal. For example, a second bit signal is indicated by “[1]” and a sixteenth bit signal is indicated by “[15].”
The latch unit 901 is a circuit which latches (holds) a state of a clock signal of a phase of each of the multi-phase clocks DU, and includes repeaters 91 and latch circuits 92, wherein each of the number of repeaters 91 and the number of latch circuits 92 is the same as the number of multi-phase clocks DU. The case in which L repeaters 91 (RP[L−1:0]) and L latch circuits 92 (DF[L−1:0]) corresponding to respective phases of multi-phase clocks DU[L−1:0] having L phases (L is a positive integer) are provided in the latch unit 901 provided in the data processing circuit 900 illustrated in FIG. 8 is shown.
In the latch unit 901 illustrated in FIG. 8, “RP” is assigned as a reference sign of the repeater 91, “DF” is assigned as a reference sign of the latch circuit 92, and a number representing each phase corresponding to a bit in the multi-phase clock DU is shown in “[ ]: brackets” following the reference signs “RP” and “DF.” Thereby, each of the repeater 91 and the latch circuit 92 indicates a phase of a corresponding multi-phase clock DU. For example, a second phase of the multi-phase clock DU is indicated by the multi-phase clock DU[1], the repeater 91 corresponding to the multi-phase clock DU[1] is indicated by the repeater RP[1], and the latch circuit 92 corresponding to the repeater RP[1] is indicated by the latch circuit DF[1].
Each repeater 91 is a buffer circuit which compensates and drives a voltage of the multi-phase clock DU of a corresponding phase, and the driven multi-phase clock DU is output to each corresponding latch circuit 92. In FIG. 8, in the solid-state imaging apparatus 800 of the related art illustrated in FIG. 7, multi-phase clocks DU[0], DU[1], . . . , DU[L−1] input from the clock generation circuit 805 disposed outside the data processing circuit 900 are driven by corresponding repeaters RP[0], RP[1], . . . , RP[L−1], respectively, and are output to corresponding latch circuits DF[0], DF[1], . . . , DF[L−1], respectively (see Japanese Unexamined Patent Application, First Publication No. 2011-166197).
Each latch circuit 92 latches (holds) a “High” or “Low” state of a clock signal of a phase of a corresponding multi-phase clock DU at an inversion timing (rising or falling timing) of a latch signal LAT representing that a voltage value of the analog signal Vin has matched a voltage value of the ramp wave Vramp, that is, that the comparator 82 has completed the comparison process, in the comparison process by the comparator 82.
Then, the latch unit 901 sequentially outputs output signals DO[L−1:0] representing states of clock signals of respective phases of the multi-phase clocks DU[L−1:0] latched in the respective latch circuits DF[L−1:0] to the digital generation unit 902 according to timings of read switch signals SW[L−1:0] corresponding to the respective latch circuits 92. In addition, the latch unit 901 outputs an output signal DO[L−1] representing the same frequency as the multi-phase clock DU[L−1] latched in the last-stage latch circuit DF[L−1] to the digital generation unit 902 as a count clock UPCLK to be used when the digital generation unit 902 generates the digital signal DOUT.
The digital generation unit 902 is a circuit which generates a digital signal DOUT obtained by binarizing a state of a phase of a multi-phase clock DU when the comparator 82 has completed the comparison process based on the output signals DO[L−1:0] sequentially output from the latch unit 901, and, for example, includes an encoder 93, a lower-order counter 94, a multiplexer 95, and a higher-order counter 96 as illustrated in FIG. 8.
The encoder 93 includes a general logic circuit, and generates a count clock BOCLK to be used by the lower-order counter 94 for a count operation to output the generated count clock BOCLK to the lower-order counter 94 based on output signals DO[L−1:0] input from the latch unit 901.
By counting the number of occurrences of the “High” state of the count clock BOCLK, the lower-order counter 94 generates a binarized lower-order side digital signal BOOUT. In addition, the lower-order counter 94 outputs a digital signal of a most significant bit within the lower-order side digital signal BOOUT as an output signal BOMSB to the multiplexer 95 connected to the higher-order counter 96.
The multiplexer 95 switches a signal to be output to the higher-order counter 96 to either the count clock UPCLK (the output signal DO[L−1]) output from the latch circuit DF[L−1] or the output signal BOMSB output from the lower-order counter 94.
The higher-order counter 96 counts the number of occurrences of the “High” state of either the count clock UPCLK or the output signal BOMSB input from the multiplexer 95. Thereby, a binarized higher-order side digital signal UPOUT is generated.
Then, the digital generation unit 902 outputs a digital signal, which is obtained by combining the higher-order side digital signal UPOUT generated by the higher-order counter 96 as the more significant bit and the lower-order side digital signal BOOUT generated by the lower-order counter 94 as the less significant bit, as the digital signal DOUT.
In this manner, in the solid-state imaging apparatus 800 of the related art, the column A/D conversion circuit 806 outputs the digital signal DOUT obtained by performing A/D conversion on the analog signal Vin corresponding to each pixel signal Vp generated by each pixel 81 of the pixel array unit 802.